Scheduling Load Operations on VLIW Machines

There continues to be a widening gap between processor speeds and memory access time. This gap is seen in systems ranging from embedded computing systems to high-performance supercomputing systems. In this paper, we present an instruction scheduling algorithm that can be targetted towards VLIW architectures commonly found in embedded systems and high-performance workstations i.e. Itanium. The goal of this paper is to present a simple instruction scheduling algorithm that does not require substantial hardware support to address the scheduling of load operations to mask the latency of delinquent loads; which are associated with high miss rates and very long average latencies. Our algorithm is named Cache Sensitive Scheduling (CSS). CSS is designed to be sensitive to the varying memory latencies of load operations, and compensate for those latencies within the instruction schedule by masking the typically long latencies of load operations with useful operations to reduce stall penalties. CSS can extend a rank-function based scheduler with two additional components to intelligently incorporate the profiled average latency of an operation, and the latencies of its predecessors. Our results show that these additional components are effective in generating schedules that are more sensitive to the latencies of load instructions. To support the selection and relative weight of our rank function components we use multivariate statistical analysis to determine the degree of correlation between our rank components and the execution time of the program. In our experiments with a VLIW parameterized compiler-simulator infrastructure using a variety of memory hierarchy configurations; we were able to achieve 20% speedups and 44% stall cycle reductions over a more conventional critical path scheduling algorithm.